Integrated circuits typically have a protection device, which is placed between an input/output (I/O) pad and its corresponding internal circuitry. The protection device prevents the circuitry from being damaged when a high transient voltage is placed on the I/O pad, such as during an electrostatic discharge (ESD) event. Protection devices are particularly important in MOS integrated circuits, because the breakdown voltage of a typical MOS transistor with a 15 nanometer gate oxide is approximately 15 volts. Therefore, electrostatic discharges, which may create voltages in excess of 1000 volts at an I/O pad, will damage MOS transistors if they are left unprotected. The protection device, however, shields the internal MOS circuitry from these excessive voltages, and thus protects the integrated circuit. However, it has been thus far impossible to build thick-field ESD protection devices on thin-film silicon on insulator (SOI) wafers, because the field oxide (FOX) isolation consumes the entire SOI layer during FOX formation.
Additionally, heat dissipation of I/O buffer circuits, such as a high voltage MOSFET, has been reported as a major obstacle for thin-film SOI material due to the poor thermal conductivity of buried oxide. The buffer circuits are typically very large and hence generate a lot of heat. Thus, poor heat dissipation poses a critical concern in the SOI technology. Additionally, a thin-film SOI MOSFET suffers from a low bipolar-snapback voltage between the source and drain electrodes. These problems effectively limit the SOI applications to a circuit or device having a lower supply voltage (V.sub.cc) than the standard 5 volts or 3.3 volts devices built on bulk silicon. With current SOI technology, a V.sub.cc greater than 2 volts will generate a runaway problem with the electron-hole pair generated in the channel region which causes the single-transistor latch. Thus, integration of 3.3 volts or 5 volts devices have been incompatible on thin-film SOI wafers because of the low breakdown voltage.